Prior art wireless communication systems are defined in the IEEE protocols for 802.11b. IEEE 802.11b is an example of a spread spectrum wireless protocol whereby a transmitter emits an isotropic or multidirectional signal including a sequence of broadband phase modulation of a carrier according to a known sequence, where the sequence is referred to as a chipping code. For 1 Mb and 2 Mb IEEE 802.11b data rates, the chipping code is a Barker code. A receiver may be placed within a reception distance from the source, and it is common for a plurality of signals to arrive at the receiver, which may be a first signal which travels a shortest path, followed by reflected signals which have path lengths which may be longer than the shortest path. Additionally, the shortest path may be through an attenuating medium, such that the shortest path does not correspond to the strongest signal. The receiver must recover this plurality of signals and apply a method of filtering before demodulating the transmitted CCK symbol into decision data. One prior art method for compensating a communications channel uses channel sounding, whereby the communications channel is characterized by sending a known signal such as a packet preamble to determine the transfer function of the channel, and then applying a combining filter function to use the channel reflections in the decision process, thereby improving the decision's reliability. This filter function is known as a channel matched filter (CMF), which in implementation may be either a separate filter or a filter combined with a feed-forward filter (FFF). Because the topology of a feed forward filter involves complex multiplications and additions, the complexity of the filter grows with the number of taps in the filter, and it is desired to minimize the number of taps in this filter. The channel matched filter and the feed-forward filter become more critical with higher data rates, since the reflections may be fixed in time duration, and the higher data rate causes degradation over a longer interval compared to the symbol rate. For example, using a 11 Mhz clock, 11 bits of a Barker code may be transmitted over 1 us for 1 Mb data rate, and the receiver must correlate a single 11 bit code to single binary value. At 11 Mb, the transmitted data is organized into 8 bit symbols, and there are 64 different CCK symbols to decode rather than two Barker codewords, with phase decoding used to recover the remaining 2 bits of data. At these higher data rates using CCK symbols, the channel is more susceptible to bit errors associated with the same multipath reflections, and greater care must be taken in the receiver signal processing leading up to demodulation of the symbols into decision data.
FIGS. 1 and 2 show the phase encoding pattern for encoding data to be transmitted into four phase terms used to form the CCK symbol. Each pair of incoming bit patterns is phase encoded according to FIG. 1. For a real-valued signal in a quadrature phase mapping, the phases may be represented as 1 (representing phase 0 phase change), j (representing a phase change of π/2), −1 (representing a phase change of π), and −j (representing a phase change of 3π/2). FIG. 2 shows 8 bit data 100 applied as an input to encoders 104a-104d, which perform phase encoding by bit pairs into four values of phase information 102, each having one of the values {1,j,−1,−j} according to the two bit (dibit) mapping shown in FIG. 1. The CCK symbol is generated using the expression of FIG. 3, whereby each of the 4 phases 102 generates the symbol C, comprising 8 chips of phase information, each chip having one of the values {1, j, −1, −j} where the phases represent the real and imaginary components according to Eulers formula:ejφ=cos(φ)+j sin(φ).
FIG. 4 shows a typical signal processing system 118 for the demodulation of DSSS CCK symbols such as an IEEE 802.11b system operating at 5.5 Mb or 11 Mb. An RF front end 120 includes an antenna 130 coupled to an RF amplifier 132 and a pair of baseband mixers 134a and 134b which mix the output of the RF amplifier 132 to baseband using quadrature outputs of local oscillator 138, which is operating at the carrier frequency of the transmitted data. The baseband quadrature signal from mixers 134a and 134b is filtered by matched low pass filters (LPF) 140a and 140b. The input to A/D converters 122a and 122b and the subsequent signal processing operate on analytic signals in quadrature form, where the quadrature signal includes the real and imaginary components in separate signal processing channels. The quadrature signal leaving the anti-aliasing, or low pass, filters 140a and 140b is sampled by A/D converters 122a and 122b and converted into a binary representation typically comprising 6 bits of in-phase and 6 bits of quadrature data. The quadrature output of the A/D converters 122a and 122b is then phase corrected 124 such that during the preamble interval of a received packet, the real (1 and −1) component of the analytic signal is maximized in the I channel, and the imaginary (j and −j) component is therefore in the Q channel. During the preamble part of the packet, the preamble is real valued, rather than complex valued, such that after phase correction 124, all of the preamble signal is maximized in the real (I) channel 125a and minimized in the imaginary (Q) channel 125b. The Q output 125b of the phase corrector 124 has no imaginary component, so the phase corrector operates to maximize the real output 125a, and later in the packet, when the coding switches to quadrature CCK, the demodulation which follows starts from a known phase rotation established during the preamble interval. The phase correction 124 may also include ongoing phase correction to compensate for phase variations over the duration of the packet, and this is often accomplished by multiplying the quadrature input with a quadrature representation of a sine function which is slowly varied to track variations in phase of the incoming signal, or using look-up tables, or any means known in the prior art. The phase corrector 124 therefore initializes and maintains the phase of the signal presented to the symbol sync 126 and CCK decision 128 over the duration of the packet. Symbol synchronization 126 converts the serial stream of CCK chips 8 into a framed series of CCK symbols of 8-chips each, each complex chip represented as 6 bits of binary data for each real and imaginary component. This framed CCK symbols are sent to the CCK decision block 128, which converts the framed CCK symbols into decisions as to which is the most likely symbol received.
Each CCK symbol, also known as a CCK codeword, to be demodulated into 8-data bits is composed of 8 CCK chips, and each CCK chip represents a particular phase encoded value of part of the 8-data bits that was transmitted, as was described earlier. Two commonly practiced techniques for deciding from the 8 CCK chips of the CCK symbol received which data was transmitted are the use of hard decisions based on individual CCK chip decisions, and soft block decisions using n=8 CCK chips at a time. In a hard decision decoder, each individual CCK chip is examined and a hard binary decision is made on each CCK chip based on a threshold parameter, and after 8 such binary decisions are independently made for an 8 chip symbol, a data decision can then be made based on mapping the 8 independent binary CCK chip decisions to a closest (measured by Hamming distance) data decision. In a soft decision decoder as used in the present invention, a block decision is made using all native I&Q sample values on the 8 CCK chips based on the euclidian distance from 8 received chips to a nearest 8 chip CCK codeword. In poor signal to noise conditions, and with a sufficiently sampled digital signal representing each CCK chip, the soft decision decoder is found to produce better code decisions than the hard decision decoder.
An additional degradation of the decision process comes in the form of multipath reflections. Multipath reflections in the communications channel result in bleeding, or spreading, of individual CCK chips, and also generate delayed copies of the CCK chips. While bleeding and delayed copies of CCK chips are all part of the same multipath reflection effect, the prior art corrections for them are handled according to whether they cause the CCK chip degradation inside or outside a symbol boundary. Multipath reflections which cause signal bleeding within a symbol block of 8 chips are known as intra-symbol bleeding, and are also referred to as inter-chip interference ICI, and can be handled within the CCK chip soft decoder, since it is using all 8 CCK chips to make a decision, while signal bleeding which transfers energy from one symbol to another symbol is known as inter-symbol interference ISI and must be corrected using Decision Feedback Equalization, as will be described later.
FIG. 5a shows the time domain smearing effect of a series of CCK chips 144a, 144b, 144c, which are convolved 7 with the Fourier transform of the channel response 145 in the time domain. The time-domain channel response 145 includes multipath reflections which cause smearing of the individual chips 144a, 144b, 144c into the received responses 146a, 146b, 146c. After multipath reflection, the separate chips are smeared in duration and for a linear system are additive such that the tail of a previous symbol becomes a post-cursor for the present symbol. The incoming chip stream to the CCK demodulator includes beginning of chip 146b adding into the tail of chip 146a, and the tail of chip 146b adding into the beginning of chip 146c, generating ICI. For clarity in showing ICI, FIG. 5a shows short duration channel smearing 145 which is approximately equal to one CCK chip duration. FIG. 5a shows ICI, however in a a typical WLAN setting, the leading edge of the channel impulse response function 145 has maximum phase change, while the tail is much longer than a single chip, and includes minimum phase components lasting many symbol lengths.
FIG. 5b shows an 8 chip CCK symbol 147, and when the symbol 147 is passed through a communications channel with the impulse response 148, a smeared symbol 149 results, which includes ICI as described in FIG. 5a, and also smears and broadens the extent of the 8 chip symbol 149 compared to the original symbol 147. When a series of such smeared CCK symbols 149 are received, information from other symbols bleeds into the current symbol, as shown in FIG. 5c. The thick line represents the smeared current symbol 154, while the dashed line represent the previous symbol 150. The resulting ISI is the sum of waveforms 150 and 154 of FIG. 5c. A feedforward filter may be used to correct the phase shifts and minor delay shifts within each chip, thereby correcting the pre-cursor effects 152 of the current symbol. A technique known as Decision Feedback Equalization (DFE) may be used to smear a previous decision using knowledge of the communication channel impulse response 148, and then invert and add the previous decision smeared symbol 151 into the current symbol 154 and previous symbol 150, thereby removing the previous symbol 150 from the symbol stream, leaving only the current symbol 154 shown as the DFE result 155 of FIG. 5d, which then contains only the current symbol 155 including ICI. Current symbol post cursor effects are of 2 types: post-cursor ISI representing interference between the current symbol 154 and a post-cursor 150 of a previous symbol, which is removed by the feedback filter of DFE which produced waveform 151, and post-cursor ICI from the current symbol. Post-cursor ICI can be removed by Maximum Likelihood Estimation (MLE), as will be described. In Decision Feedback Equalization, once the current symbol decision has been made and presented as decision data, it is converted back into an 8 chip symbol, smeared with the minimum phase part of the channel impulse response, and the smeared version of this previous symbol is subtracted from the current symbol, which improves the decision for the current symbol. In Maximum Likelihood Estimation, a soft decision (decision based on euclidian distance based on a block of 8 chips) is made on the current symbol based on subtracting the ICI component for all possible 256 current symbols from the current symbol, which has the effect of increasing the detector response for the correct symbol, and comparatively reducing the detector response for incorrect symbols. By making soft decisions based on subtracting the ICI from all possible current symbols, the accuracy of the decision is improved, shown as cleaned up waveform 157 of FIG. 5e. 
FIG. 6 shows the block diagram for a prior art block decision feedback equalizer such as described in FIGS. 6 and 7 of U.S. Pat. No. 6,233,273 by Webster et al. Incoming quadrature CCK symbols are presented at input 160 to a feedforward filter 162, which performs phase compensation principally on the leading edge of each of the 8 chips of the symbol where the signal energy and phase errors are highest. This phase compensation improves the accuracy of demodulation of the current symbol where only DFE is used. Block 168 makes a CCK symbol decision 170, as will be described later. The decision data 170 is converted back to a CCK symbol of 8 chips in block 169 and is smeared to match the original channel distortion using feedback filter 166, and is presented to the subtractor 164, which restores the leading edge of each chip of the chip stream, as was described in FIGS. 5c and 5d. In the implementation of FIG. 6, feed forward filter 162 has a small number of taps, since it is used principally to perform phase correction on the comparatively short leading edge of each chip, while the decision feedback filter 166 operates over the comparatively longer temporal range, but minimum phase region of an entire symbol by smearing the previous symbol to match the channel reflections and subtracting this smeared previous symbol from the present symbol. Together, the feedforward filter 162 and feedback filter 166 constitute a transversal filter trained to equalize the channel impulse response of the communications channel. In this manner, the feedforward filter 162 reduces symbol interference due to pre-cursor effects, the feedback filter 166 reduces symbol interference due to post-cursors from previous symbols, and the maximum likelihood estimation removes the ICI effects from the current symbol.
FIG. 7 shows a prior art implementation 190 of the CCK symbol decision block 168 of FIG. 6. Examining one of the four blocks, a simple Fast Walsh Transform (FWT) 182 operates on the incoming CCK symbol 172, and produces a complex-valued output based on transforming the incoming CCK chip 172 with a particular butterfly φ2. Each of the FWT blocks 182, 184, 186, 188 performs the Fast Walsh Transform using the incoming CCK chip and a unique butterfly value of φ2={1,j,−1,−j}, for 174, 176, 178, and 180, respectively. The output of each Fast Walsh Transform block 182, 184, 186, 188 is 16 complex values, and for the four FWT blocks 182, 184, 186, 188 in aggregate, one of the 64 outputs will have a maximum magnitude. The FWT output which is maximum magnitude will determine the CCK symbol decision, and this one of 64 selection can be decoded to generate 6 bits of data. Examining the real (I), and imaginary (Q) values from the maximum valued output will further indicate which of the four phases {1,j,−1,−j} is present, which will result in 2 additional bits of data, thereby generating an 8 bit decision data value.
FIG. 8 shows a Fast Walsh Transform (FWT) block such as one of FWT blocks 182, 184, 186, 188 of FIG. 7. CCK symbols are presented to input 222 accompanied by one of the four butterfly phases φ2={1,j, −1, −j} at input 232. The simple FWT 220 comprises a butterfly configuration of multiplying the phase φ2 232 with every alternating bit of the incoming symbol, followed by a series of adders which sum the resulting outputs after multiplication by {1,j,−1,−j}, as shown. For example, adder 226a adds b1 to b0*ejφ2, where ejφ2 is from the set {1, j, −1, −j} as was described 9 earlier. The output of each adder 226a, 226b, 226c, 226d is multiplied by {1,j,−1,−j} according to the legend shown in FIG. 8 and these complex results are forwarded to the next stage as shown. The result of the series of additions of these results is seen in the outputs of the 16 adders 230a through 230p, only one of which will have a maximum value for a given input symbol. For a given symbol in the subset associated with a particular phase 232, one of the adder outputs 230a through 230p will have a maximum value, corresponding to the decoded symbol. When four of the simple FWT blocks 220 are provided with the same input symbol 222 and each of the four phases 232, all 64 (16*4) code symbols are available for decoding, and a decision on the set of 64 symbols is made based on the largest value at the outputs of the adders in each FWT block 220, and the phase of this output provides 2 additional bits of data.
As was described in the FIGS. 5a through 5d and FIG. 6, the decision feedback equalizer can improve the decision made on a current symbol in poor signal to noise conditions. Once the previous symbol has been decided, it can be smeared with a filter which has characteristics similar to the communications channel, and then inverted and added as symbol 151 of FIG. 5c to the current symbol 154, thereby removing the post-cursor effects of the previous symbol 150 on current symbol 154. It should also be noted that the decision feedback filter 166 may have as many taps as is required to subtract as many previous symbols from the current symbol as the taps of the filter permit. For the case of a feedback filter 166 with 16 taps, it is possible to subtract the effects of two 8 chip previous symbols which have added into the current symbol. It is also desirable to remove the intra-symbol (inter-chip interference ICI) interference of one chip smearing with another chip within a symbol, as shown in FIG. 5a. This can be done by making soft decisions on the entire symbol after subtracting the chip smearing ICI effect. FIG. 9 shows a CCK symbol demodulator which performs both decision feedback equalization (DFE) (also referred to as pre-equalization), as well as maximum likelihood symbol estimation (MLE), also referred to functionally in FIG. 9 as a post-equalizer function 312. There are many ways of realizing the general MLE and DFE functionality shown in FIG. 9, but one such realization is described in FIGS. 13 and 14 of prior art U.S. Pat. Nos. 6,690,715 and 6,233,273 by Webster et al. In FIG. 9, incoming CCK chips 286 are presented as a digital stream of complex data, sampled with approximately 6 bit data width. This complex-valued digital data may first be combined with a channel matched filter (not shown) performing rake combining, the output of which is filtered by a feed-forward filter (FFF) 288, which performs maximum phase compensation on the incoming signal, and passes the output as signal 289 to a serial-parallel converter 290, which converts the serial stream of data into framed 8 complex values, representing a current CCK symbol 291 comprising 8 CCK chips. In addition to the CCK symbol input 291, previous decision feedback symbol input 304 is provided for pre-equalization (removal of previous symbol post-cursors from the current symbol), and the output of this stage is fed to demodulator 314 which performs an FWT and current symbol subtractor 296 subtracts the 64 post-equalization symbol inputs for maximum likelihood estimates which remove intra-symbol interference ICI (shown in FIG. 5a), where the intra-symbol interference correction is generated by post-equalizer 312. Examining the decision feedback equalization path from the output 305, the previous decision data 305 is converted to a CCK symbol of 8 chips in converter 300, which produces a CCK symbol 301 corresponding to 8 complex chip phase values of I and Q as is done in CCK encoding for transmission of data. These 8 complex phase values 301 I and Q channels are passed through 8 feedback filters 302-1 through 302-8 which simulate the minimum phase and maximum delay component of the channel impulse response, as was described earlier. The length of the feedback filter 302-1 through 302-8 governs how many previous symbols of contributions may be removed from the current symbol, and in the case of a length flt_len=16 taps, a channel response function which includes signal energy bleeding from two previous CCK symbols may be subtracted from the current CCK symbol.
The output of the feedback filters 302-1 through 302-8 produce a symbol comprising 8 complex channel-equalized chip values for the previous decision 304, which are subtracted from the current symbol 291 by the previous decision subtractor 292, which subtracts the previous decision smeared symbol 304 from the current CCK symbol 291, as was described for block 164 of FIG. 6. Simplifying the operation by ignoring the effect of the current symbol subtractor 296, Fast Walsh Transform 294 converts the 8 complex values for a decision feedback equalized symbol into 64 complex outputs, from which the largest magnitude output would represent the demodulated symbol, thereby extracting 6 bits of data, and the phase position of the largest magnitude output {1,j,−1,−j} would provide an additional 2 bits of data, generating an 8 bit decision data value. Now including consideration of the operation of the post-equalizer processor 312 and current decision subtractor 296, it may be understood that the subtraction of post-cursor ICI from chips within the current symbol smearing together may be done prior to the FWT 294 in the time domain, as was done with previous decision subtractor 292, or it may be done after the FWT 294 in the phase domain, since the FWT is a linear operation. This may be done as long as the value to be subtracted is in the symbol time domain at the input of the FWT, or transformed into the phase domain if subtracted in the post-FWT phase domain. Considering further the implementation of the post-FWT current symbol subtractor 296 as shown in FIG. 9, the post-equalizer 312 provides 64 post-FWT phase domain, channel compensated symbol correction values 285 which represent corrections to all of the possible current CCK symbols in the post-FWT phase domain. These possible CCK symbol corrections 285 are presented to current symbol subtractor 296 as 64 complex values. Each of the 64 complex outputs 297 is expanded to four using 1,j,−1 and −j with index variable k 299. The biggest picker 298 has 256 complex FWT values stored for this input symbol 291, and one of the 256 values will have maximum real part. This maximum output will include the post-FWT phase domain current symbol, with the post-cursor ISI of the previous decision (shown as 150 of FIG. 5c) removed by the pre-equalizer smeared previous decision 304 which provided symbol 151 of FIG. 5c, and the ICI of the chips of the current symbol bleeding into each other removed by post-equalizer 312 outputs 285 iterated over the four values of k. The index of the largest expanded output with largest 9 real-part would give the 8-data bit decision data.
Post-equalization value generator 312 produces the error generated by inter-chip interference (ICI) in the symbol, converts it into the post-FWT phase domain by taking the 64 CCK codewords 280-1 through 280-64, passing each of the CCK codewords through an identical feedback filter 282-1 through 282-64 which generates the ICI correction value, and each of these is passed through a correlator 284-1 through 284-64 for converting the symbol to the post-FWT phase domain. In this manner, the ICI for each possible received symbol is subtracted, cleaning up the FWT output corresponding to the current symbol compared to the other outputs, thereby generating an improved decision for the correct symbol.